Flow-aware Reconfigurable Multi-lane Multi-symbol Reed-Solomon Decoder Architecture for FPGA Implementation

This paper proposes a multi-lane Reed–Solomon (RS) decoder architecture designed for high-throughput video streaming systems under practical operating conditions. The proposed system consists of a parallel RS decoding core capable of processing multiple symbols per cycle, a gearbox for symbol packing, and lane-wise FIFOs. By utilizing elastic buffers and a credit-based scheduling method, the system can manage backpressure and lane misalignment. Consequently, it achieves a coding efficiency of 93.7%, a throughput of approximately 3.0 Gb/s, and an estimated ideal input-transfer time of 1.25 ms for a 4-Mbit encoded workload, while maintaining stable operation. These results demonstrate the clear advantages of a multi-lane architecture for accelerating data processing. The results also indicate strong error-correction performance within the operational BER range, highlighting the effectiveness of the proposed system-level co-design approach.